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Electronic design automation (EDA) is the category of tools for designing and producing electronic electronic design automation systems ranging from printed circuit boards (PCBs) to integrated circuits. This is sometimes referred to as ECAD (electronic computer-aided design).
The term EDA is also used as an umbrella term for computer-aided engineering, computer-aided design and computer-aided manufacturing of electronics in the discipline of electrical engineering. This usage probably originates in the IEEE Design Automation Technical Committee.
EDA has rapidly increased in importance with the continuous scaling of semiconductor technology. (See: Moore's Law.) The largest segment of EDA users are chip designers at semiconductor companies, who design chips using EDA software. Foundry operators (who actually run the fabs) and design-service companies also use EDA software to evaluate an incoming design for manufacturing readiness.
Product areas (incomplete)
EDA is divided into many (sometimes overlapping) sub-areas. They mostly align with the path of manufacturing of the chips from design to mask generation.
- Design and Architecture: design the chip's schematics, output in Verilog, VHDL, SPICE and other formats.
- Floorplanning: The preparation step of creating a basic die-map showing the expected locations for logic gates, power & ground planes, I/O pads, and hard macros. (This is analogous to a city-planner's activity in creating residential, commercial, and industrial zones within a city block.)
- Logic synthesis: translation of a chip's (abstract) RTL-description (Verilog or VHDL) into a discrete netlist of logic-gate (boolean-logic) primitives
- Behavioral Synthesis, High Level Synthesis or Algorithmic Synthesis: This takes the level of abstraction higher and allows automation of the architecture exploration process. It involves the process of translating an abstract behavioral description of a design to synthesizeable RTL. The input specification is in languages like behavioral VHDL, algorithmic SystemC, C++ etc and the RTL description in VHDL/Verilog is produced as the result of synthesis.
- Intellectual property blocks: provide pre-programmed design elements.
- Simulation: simulate circuit's work and detect any shortcomings
- Transistor Simulation – low-level transistor-simulation of a schematic/layout's behavior, accurate at device-level
- RTL Simulation – digital-simulation of an RTL or gate-netlist's digital (boolean 0/1) behavior, accurate at boolean-level
- Behavioral Simulation – high-level sim of a design's architectural operation, accurate at cycle-level or interface-level
- Formal verification: algorithmic-comparison between a chip's RTL-description and synthesized gate-netlist, to ensure equivalency at the logical level
- Place and route, PR: (for digital devices) tool-automated placement of logic-gates of the synthesized gate-netlist, then subsequent wiring of the gates' signal and power terminals.
- Transistor layout: (for analog/mixed-signal devices), sometimes called polygon pushing – a prepared-schematic is converted into a layout-map showing all layers of the device (doping, interconnect)
- Physical verification, PV: checking if design is physically manufacturable and resulting chips will not have any functioning preventing physical defects and meet original specifications
- Design rules checking, DRC – checks number of rules of geometric and connectivity nature specified by manufacturer
- Layout versus schematic, LVS – checks if designed chip layout matches schematics from specification
- Parasitic device extraction, RCX – extracts parasitic resistors (PRE), and often capacitors (RCX), and sometimes inductors, inherent in the chip layout
- Mask data preparation, MDP: generation of actual lithography photomask used to physically manufacture the chip
- Resolution enhancement techniques, RET – methods of increasing of quality of final photomask
- Optical proximity correction, OPC – up-front compensation for diffraction and interference effects occurring later when chip is manufactured using this mask
- Mask generation – generation of flat mask image from hierarchical design
- Manufacturing Test
- design for test, DFT – adds logic-structures to a gate-netlist, to facilitate post-fabrication (die/wafer) defect testing
- automated test pattern generation, ATPG – generates pattern-data to systematically exercise as many logic-gates as possible
Largest companies
Company |
Location |
Market Value |
Logo |
|---|
Cadence Design Systems |
San Jose, California |
$3.5 billion |
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Synopsys |
Mountain View, California |
$2.5 billion |
|
Mentor Graphics |
Wilsonville, Oregon |
$1.0 billion |
|
Magma Design Automation Inc |
Santa Clara, California |
$387 million |
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Related articles
- Circuit Design
- List of EDA companies
- List of CAD companies
- Fabrication (semiconductor)
- GDSII
- OASIS
- OrCAD
- SPICE
- Advanced Design System
External links
- EDA Consortium
- EDA Industry Working Groups – Non-Profit standards organization
- EDA Cafe – Commercial website trying to serve as a portal to the EDA industry
- DAC – The Design Automation Conference is a premier event for Electronic Design Automation
Open source EDA tools
- Open Collector – a news site for Free EDA software
- OpenTech CD ROM – collects several hundred tools
- gEDA – GPLed EDA tools
- Magic 7 – A popular open-source IC design tool
- Berkeley Chipmunk – A historic set of tools.
- The Electric VLSI Editor
- LASI – Integrated Circuit CAD for Windows
- OPENCORES.ORG – Predesigned, GPLed pieces of logic for ICs
- For open source versions of logic design languages, see the languages, e.g. See VHDL, Verilog
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Electronics Topics
The field of electronics is the study and use of systems that operate by controlling the flow of electrons or other electrically charged particles in devices such as thermionic valves and semiconductors. The design and construction of electronic circuits to solve practical problems is part of the fields of electronic engineering, and the hardware design side of computer engineering. The study of new semiconductor devices and their technology is sometimes considered as a branch of physics.
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